台積電的5奈米已經幫HPC做優化 - 股票

By Lauren
at 2019-11-03T20:26
at 2019-11-03T20:26
Table of Contents
1.原文連結:
https://fuse.wikichip.org/news/2879/tsmc-5-nanometer-update/
2.原文內容:
台積電在最近的 ARM Tech Con提到
7奈米製程,是先對 low-power優化後,再對HPC做優化
但5奈米製程已經同時對 low-power mobile
和 HPC (high performance computing)進行優化
2020年進入N5 五奈米製程
N5 五奈米 vs 七奈米製程(DUV)
同樣的功耗,速度增加 15%
同樣的速度,能耗降低 30%
邏輯密度 1.8倍
https://i.imgur.com/78l6YNs.png
2021年進入 N5P 製程
N5P 相較於N5
效能增加 7%
或耗能降低15%
https://i.imgur.com/Qu2OeO5.png
3.心得/評論:
AMD應該很開心,台積電已經在幫他們Tune五奈米的效能了
--
https://fuse.wikichip.org/news/2879/tsmc-5-nanometer-update/
2.原文內容:
台積電在最近的 ARM Tech Con提到
7奈米製程,是先對 low-power優化後,再對HPC做優化
但5奈米製程已經同時對 low-power mobile
和 HPC (high performance computing)進行優化
2020年進入N5 五奈米製程
N5 五奈米 vs 七奈米製程(DUV)
同樣的功耗,速度增加 15%
同樣的速度,能耗降低 30%
邏輯密度 1.8倍
https://i.imgur.com/78l6YNs.png
2021年進入 N5P 製程
N5P 相較於N5
效能增加 7%
或耗能降低15%
https://i.imgur.com/Qu2OeO5.png
3.心得/評論:
AMD應該很開心,台積電已經在幫他們Tune五奈米的效能了
--
Tags:
股票
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